Caio Raphael

ISA is the formal contract between software and a CPU.
It defines:
- available instructions (ADD, MOV, etc.)
- registers and their roles
- memory addressing modes
- binary encoding of instructions
- calling conventions (partially)
- privilege levels
It does not define:
- pipeline depth
- cache sizes
- branch predictor
- microarchitecture details
ISA = what the CPU promises
Microarchitecture = how the CPU delivers
Two CPUs can implement the same ISA and run the same binaries while having completely different internal designs.
Example ISAs
- x86-64
- ARM
- RISC-V

CISC is a CPU design philosophy that favors powerful, complex instructions.
Original goals (1970s)
- reduce number of instructions per program
- make compilers simpler
- save memory (important at the time)
Typical characteristics
- variable-length instructions
- many addressing modes
- instructions that perform multiple operations
- memory-to-memory operations possible
- irregular encoding
One instruction, many internal steps.
Example ISA
- x86
Example sequence (conceptual):
```
add [mem1], [mem2]
```

RISC is a philosophy favoring simple, uniform instructions.
Original goals (1980s)
- make pipelines efficient
- enable higher clock speeds
- simplify hardware
- rely more on the compiler
Typical characteristics
- fixed instruction width
- load/store architecture
- many general-purpose registers
- simple addressing modes
- usually one operation per instruction
Example ISAs
- ARM
- MIPS
- RISC-V
Example sequence:
- Instead of one complex instruction:
```
ldr r0, [mem1]
ldr r1, [mem2]
add r0, r0, r1
str r0, [mem1]
```
- More instructions, but each is simple and predictable.